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ADM1041
Table 40. Register 2Bh, Status2 Mirror. Power-On Default 00h.
These flags are cleared by a register read, provided the fault no longer persists.
Bit No.
7
6
5
4
3
2
1
0
Name
Share_OKb_L
orfetokb_L
reverseokb_L
V DD OK b_L
gndokb_L
intrefokb_L
extrefokb_L
vddov_L
R/W
R
R
R
R
R
R
R
R
Description
share fault
ORFET fault
reverse fault
vdd fault
gnd fault
intref fault
extref fault
vddov
Note that latched bits are clocked on a low-to-high transmission only. Also note that these
register bits are cleared when read via the SMBus, except if the fault is still present. It is
recommended to read the register again after faults disappear to ensure reset.
Table 41. Register 2Ch, Status3 Mirror. Power-On Default 00h
These flags are cleared by a register read, provided the fault no longer persists.
Bit No.
7
6
5
4
3
2
1
0
Name
m_acsns_rb_L
m_pson_rb_L
m_penok_rb_L
m_psonok_rb_L
m_DC_OK_rb_L
ocpf
PULSE_OKb_L
fault
R/W
R
R
R
R
R
R
R
R
Description
AC_OK fault
PSON fault
PEN fault
PS ON LINK fault
DC_OK fault
ocpf fault
pulse fault
fault latch
Note that latched bits are clocked on a low-to-high transmission only. Also note that these
register bits are cleared when read via the SMBus, except if the fault is still present. It is
recommended to read the register again after the faults disappear to ensure reset.
MANUFACTURING DATA
Table 42.
Register 81F0h
Register 81F1h
Register 81F2h
Register 81F3h
Register 81F4h
Register 81F5h
Register 81F6h
Register 81F7h
Register 81F8h
Register 81F9h
Register 81FAh
Register 81FBh
Register 81FCh
Register 81FDh
Register 81FEh
Register 81FFh
PROBE1_BIN
PROBE2_BIN
FT_BIN
PROBE1_CHKSUM
PROBE2_CHKSUM
FT_CHKSUM
QUAL_PART_ID
Probe 1 cell current data (integer)
Probe 1 cell current data (two decimal places)
Probe 2 cell current data (integer)
Probe 2 cell current data (two decimal places)
Final test cell current data (integer)
Final test cell current data (two decimal places)
Probe X coordinate
Probe Y coordinate
Wafer number
Rev. A | Page 51 of 64
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